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--- fpga_phy_zigbee [2017/12/13 12:05] – [Transmitter] ooubejja
+++ fpga_phy_zigbee [2017/12/14 16:25] (current) – [What's new here ?] ooubejja
@@ Line 13: / Line 13: @@
 As seen in the previous tutorials, operations such as FFT, MUX/DEMUX, encoding, modulation,... are processed via GNU Radio blocks all over the flow graph. In other words, the transmitted waveform is "soft shaped" by GNU Radio.
 The goal of this tutorial is to transmit IEEE 802.15.4 packets with a "Hard" transmitter, it means that the waveform is generated by the PicoSDR, by taking a ''.hex'' file as an input and processing it through an FPGA design, using [[http://whatis.techtarget.com/definition/IP-core-intellectual-property-core|IP cores]] written in hardware description language (HDL) code.
-In this tutorial, we will see how to transmit and receive IEEE 802.15.4 packets using a .hex file as an input and a [[custom Bitstream]] of a IEEE 802.15.4 PHY Layer Transmitter targeting the Xilinx FPGA [[https://www.google.fr/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwi_197x2-bXAhUHrRQKHXmRCWQQFggxMAE&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fdata_sheets%2Fds150.pdf&usg=AOvVaw0Z12Npy0fD0V2OybYMhTkH|Virtex6]] of the [[https://www.nutaq.com/products/picosdr|PicoSDR]]
+In this tutorial, we will see how to transmit and receive IEEE 802.15.4 packets using a .hex file as an input and a custom Bitstream of a IEEE 802.15.4 PHY Layer Transmitter targeting the Xilinx FPGA [[https://www.google.fr/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwi_197x2-bXAhUHrRQKHXmRCWQQFggxMAE&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fdata_sheets%2Fds150.pdf&usg=AOvVaw0Z12Npy0fD0V2OybYMhTkH|Virtex6]] of the [[https://www.nutaq.com/products/picosdr|PicoSDR]]
 ----
@@ Line 21: / Line 21: @@
 We will need some blocks of the module [[https://github.com/CorteXlab/gr-cortexlab|gr-cortexlab]]. Normally, if you followed the previous tutorials (highly suggested!), you might have started by installing [[building_a_toolchain|The FIT/CorteXlab Toolchain]], which automatically installs this module.
-==== Download bitstream ====
+==== Find the Bitstream ====
-In order to use the FPGA Transmitter design, we will have to load the custom bitstream on the transmitter node(s). The Bitstream can be found [[here]]
+In order to use the FPGA Transmitter design, we will have to load the custom Bitstream on the transmitter node(s). The Bitstream is loaded in the Airlock server of CorteXlab, and can be found in :
-The receiver node(s) will run the default bitstream (Pass-through design)
+''/cortexlab/fpga/pico_tx802154_sx315.bit''
+Copy the file in your main directory :
+<code>
+you@srvairlock:~$ cp /cortexlab/bitstreams/pico_tx802154_sx315.bit .
+</code>
+//The receiver node(s) will run the default Bitstream (Pass-through design)//
 ----