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--- fpga_phy_zigbee [2017/12/06 15:37] – [Transmitter] ooubejja
+++ fpga_phy_zigbee [2017/12/14 16:25] (current) – [What's new here ?] ooubejja
@@ Line 1: / Line 1: @@
  --- //[[othmane.oubejja@inria.fr|Othmane Oubejja]] 2017/11/30 17:33//
-! UNDER CONSTRUCTION !
 {{ :under-128.png?100 |}}
@@ Line 9: / Line 8: @@
-In this tutorial we will focus on the PHY layer exclusively and, in order to encode/decode packets, we will use a custom and (very) light MAC frame structure using [[https://en.wikipedia.org/wiki/Intel_HEX|Intel HEX]] data format, **which has nothing to do with the native 802.15.4 MAC Frame Structure !**
+In this tutorial we will focus on the PHY layer exclusively and, in order to encode/decode packets, we will use a (very) light MAC frame structure using [[https://en.wikipedia.org/wiki/Intel_HEX|Intel HEX]] data format. (//which has nothing to do with the native 802.15.4 MAC Frame Structure !//)
 ==== What's new here ? ====
 As seen in the previous tutorials, operations such as FFT, MUX/DEMUX, encoding, modulation,... are processed via GNU Radio blocks all over the flow graph. In other words, the transmitted waveform is "soft shaped" by GNU Radio.
 The goal of this tutorial is to transmit IEEE 802.15.4 packets with a "Hard" transmitter, it means that the waveform is generated by the PicoSDR, by taking a ''.hex'' file as an input and processing it through an FPGA design, using [[http://whatis.techtarget.com/definition/IP-core-intellectual-property-core|IP cores]] written in hardware description language (HDL) code.
-In this tutorial, we will see how to transmit and receive IEEE 802.15.4 packets using a .hex file as an input and a [[custom Bitstream]] of a IEEE 802.15.4 PHY Layer Transmitter targeting the Xilinx FPGA [[https://www.google.fr/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwi_197x2-bXAhUHrRQKHXmRCWQQFggxMAE&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fdata_sheets%2Fds150.pdf&usg=AOvVaw0Z12Npy0fD0V2OybYMhTkH|Virtex6]] of the [[https://www.nutaq.com/products/picosdr|PicoSDR]]
+In this tutorial, we will see how to transmit and receive IEEE 802.15.4 packets using a .hex file as an input and a custom Bitstream of a IEEE 802.15.4 PHY Layer Transmitter targeting the Xilinx FPGA [[https://www.google.fr/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0ahUKEwi_197x2-bXAhUHrRQKHXmRCWQQFggxMAE&url=https%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fdata_sheets%2Fds150.pdf&usg=AOvVaw0Z12Npy0fD0V2OybYMhTkH|Virtex6]] of the [[https://www.nutaq.com/products/picosdr|PicoSDR]]
 ----
@@ Line 22: / Line 21: @@
 We will need some blocks of the module [[https://github.com/CorteXlab/gr-cortexlab|gr-cortexlab]]. Normally, if you followed the previous tutorials (highly suggested!), you might have started by installing [[building_a_toolchain|The FIT/CorteXlab Toolchain]], which automatically installs this module.
-==== Download bitstream ====
+==== Find the Bitstream ====
-In order to use the FPGA Transmitter design, we will have to load the custom bitstream on the transmitter node(s). The Bitstream can be found [[here]]
+In order to use the FPGA Transmitter design, we will have to load the custom Bitstream on the transmitter node(s). The Bitstream is loaded in the Airlock server of CorteXlab, and can be found in :
-The receiver node(s) will run the default bitstream (Pass-through design)
+''/cortexlab/fpga/pico_tx802154_sx315.bit''
+Copy the file in your main directory :
+<code>
+you@srvairlock:~$ cp /cortexlab/bitstreams/pico_tx802154_sx315.bit .
+</code>
+//The receiver node(s) will run the default Bitstream (Pass-through design)//
 ----
@@ Line 50: / Line 57: @@
   - === TX Flowgraph in GRC (ieee802154_tx_pico.grc)===
-The PicoSDR needs some initializing stuff to be done, here is what is new comparing to the previous tutorials :
+The PicoSDR needs some initializing stuff to be done :
-* Add and configure these blocks:
+* Add and configure these blocks as seen in previous PicoSDR tutorials :
  * **RTDEx Sink**
   * ATTENTION : **Channel** parameter has to be set to **__3__** as in the previous image. That's the only channel that allows access to the custom design.
- * **Radio420x**
-  * Set CR1 value to 0 to enable the transmitter
  * **Custom Register** (CR 1 & 4)
@@ Line 64: / Line 68: @@
   * Set CR1 value to 0 to enable the transmitter
   * Set CR4 value to 0 to disable MIMO synchronization
+ * **Radio420 **
+  * The Radio420x is a Multimode SDR [[https://en.wikipedia.org/wiki/FPGA_Mezzanine_Card|FMC]] RF transceiver. PicoSDR 2x2 contains 2 Radio420M modules which are MIMO capable //(M for MIMO, pretty smart, huh ?)//. It is mandatory to initialize BOTH radio cards, even if only 1 is used. So, since our device contains 2 Radio420M transceivers, it means we will have 2 ''Radio420 TX'' blocks and 2 ''Radio420 RX'' blocks. Here is a [[https://www.nutaq.com/sites/default/files/Radio420x_V1.3_03_24_2014_web.pdf|product sheet]] for more info.
+  * To be short, add 2 ''Radio420 TX'' blocks and 2 ''Radio420 RX'' blocks
+  * Now, we only need one transmitter per node, so make sure to enable only the Radio420 TX of Card 1, and set the gain values as following :
+{{ :radio420.png?250 |}}
+  * For the 3 remaining ''Radio420'' blocks, we only need to disable them by setting the __Enable__ parameter to __False__
 //If you don't get this part, have a look [[from_gnuradio_to_cortxlab_pico|here]].//
-There isn't that much done in here since all baseband processing is done by the FPGA. All that is left is to connect a ''**File Source**'' block to the ''**RTDEx Sink**'' block, and specify the absolute path to your ".hex" file in ''**File Source**'' block parameters :
+There isn't that much left in here since all baseband processing is done by the FPGA. All you have to do now is to connect a ''**File Source**'' block to the ''**RTDEx Sink**'' block, and specify the absolute path to your ".hex" file in ''**File Source**'' block parameters :
 {{ :filesource.png?400 |}}
-The final flow-graph should look like this :
+The final flow-graph of your transmitter should look like this :
 {{ :ieee802154_tx_pico.grc.png?400 |}}
@@ Line 86: / Line 100: @@
 ==== Receiver (ieee802154_rx_pico.grc)====
+not finished
 {{ :ieee802154_rx_pico.grc.png?400 |}}
 ==== Generate .py files ====
@@ Line 141: / Line 159: @@
 ===== Upload files and run the experiment =====
+The experiment directory should look like this by now :
 <code>
 ...
-├── pico_zigbee.task
 ├── pico_zigbee
 │   ├── frame_fpga.hex
@@ Line 153: / Line 171: @@
 │   ├── scenario.yaml
 │   ├── pico_tx802154_sx315.bit
 ...
 </code>
-The .grc files are not needed to create the task, but if ever you want to change/debug your flow graph it's more practical to do it in GRC rather than reading the generated .py file.
+The ''.grc'' files are not needed to create the task, but if ever you want to change/debug your flow graph it's more practical to do it in GRC rather than reading the generated .py file.
+Now you have to [[exp_upload|upload the files]] to Airlock server and [[reserve|book the testbed]].
+Create the task :
+<code>
+you@srvairlock:~$ minus task create path/to/the/folder/pico_zigbee
+</code>
+And submit it :
+<code>
+you@srvairlock:~$ minus task submit pico_zigbee.task
+</code>
@@ Line 163: / Line 195: @@
 ===== Check results =====
-Wait until the task is finished, proceed to extract results of the RX node(s). In our case it's the Node31 only.
+Check the experiment status :
+<code>
+you@srvairlock:~$ minus testbed status
+</code>
+And when the task is finished you should get this message :
+<code>
+you@srvairlock:~$ minus testbed status
+num total tasks:   xxxx
+num tasks waiting: 0
+num tasks running: 0
+tasks currently running:
+  (none)
+</code>
+Then proceed to extract results of the RX node(s). In our case it's the Node31 only.
 The file tree should look like this :
@@ Line 181: / Line 230: @@
 │   │   │   │   ├── scenario.yaml~
 │   │   │   │   ├── pico_tx802154_sx315.bit
-impact_instr.txt
+│   │   │   │   ├── impact_instr.txt
-frame_fpga.hex
+│   │   │   │   ├── frame_fpga.hex
-_impactbatch.log
+│   │   │   │   ├── _impactbatch.log
-stderr.txt
+│   │   │   │   ├── stderr.txt
-__stdout.txt__
+│   │   │   │   ├── stdout.txt
 ...