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| doc [2025/07/09 11:59] – [Octoclocks] lcardoso | doc [2025/07/09 12:06] (current) – lcardoso | ||
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| A hierarchy of octoclocks allow the reference and timing distribution to all USRPs in CorteXlab. All cables are of same length (5m between master and slave octoclocks and 10m between slave octoclocks and USRPs). The connection layout is as shown below. The octoclock 0 is the master and the octoclocks 1-4 are the slave ones. | A hierarchy of octoclocks allow the reference and timing distribution to all USRPs in CorteXlab. All cables are of same length (5m between master and slave octoclocks and 10m between slave octoclocks and USRPs). The connection layout is as shown below. The octoclock 0 is the master and the octoclocks 1-4 are the slave ones. | ||
| - | {{::distrubution_reference_octoclock.png?800|}} | + | {{::octoclocks.png?800|}} |
| ==== Timing measurements in the CorteXlab room: ==== | ==== Timing measurements in the CorteXlab room: ==== | ||
doc.txt · Last modified: by lcardoso